As semiconductor chips become more and more widely used, more factors may cause electrostatic damage to semiconductor chips. In existing semiconductor chip designs, an electrostatic discharge (ESD) protection circuit is often adopted to reduce damages to semiconductor chips. Currently, the designs and the applications of existing ESD protection circuits include gate grounded NMOS (GGNMOS) protection circuit, shallow trench isolation (STI) diode protection circuit, gated diode protection circuit, laterally diffused MOS (LDMOS) protection circuit, bipolar junction transistor (BJT) protection circuit, etc.
FIG. 1 shows a schematic cross-section view of an existing GGNMOS protection circuit. Referring to FIG. 1, the ESD protection circuit includes a substrate 10, a P-type well region 11 formed in the substrate 10, a gate structure 12 formed on the surface of the P-type well region 11, an N-type source electrode 13 and an N-type drain electrode 14 formed in the P-type well region 11 on the two sides of the gate structure 12. The N-type source electrode 13, the P-type well region 1, and the N-type drain electrode 14 together form a parasitic NPN transistor. Specifically, the source electrode 13 is the emitter of the parasitic transistor, the drain electrode 14 is the collector of the parasitic transistor, and the P-type well region 11 is the base region of the parasitic transistor. Further, the source electrode 13, the P-type well region 11, and the gate electrode of the gate structure 12 are grounded, and an electrostatic voltage is applied to the drain electrode 14.
According to existing ESD device designs, because the electrostatic current may often be large, a number of transistors are usually used and connected in parallel with each other in order to improve the ESD protection ability of the device.
However, conventional ESD protection devices may still not be able to provide sufficient ESD protection. The disclosed electrostatic discharge protection devices and fabrication methods thereof are directed to solve one or more problems set forth above and other problems in the art.